Optimization of technological choices in SMT with respect to thermomechanical stresses

With the development of large scale integration technologies, leading to large size chips, a large increase of package dimensions and of number of leads, with thinner and thinner pitch, is observed in SMT. This evolution clearly involves higher criticity at the solder joint level, when electronic boards are submitted to thermal variations. The thermal expansion mismatch between the different parts of the structure, including package, lead, solder and substrate may generate high level stresses in the solder, leading to mechanical fatigue, cracks and failures. In order to evaluate and to compare the effects of lead stiffness on the solder behaviour of different types of assemblies, we have proposed a simple analytical model for each type of lead, taking in account the geometry of the components (package and leads), the Young modulus of the lead material, and the variation of temperature