Title :
Technology-circuit convergence for full-SOC platform in 28 nm and beyond
Author :
Arnaud, F. ; Colquhoun, S. ; Mareau, A.L. ; Kohler, S. ; Jeannot, S. ; Hasbani, F. ; Paulin, R. ; Cremer, S. ; Charbuillet, C. ; Druais, G. ; Scheer, P.
Author_Institution :
STMicroelectron., Crolles, France
Abstract :
In this paper, we present a process/design co-optimization methodology for a full-SOC platform based on 28nm LP CMOS technology with high-k metal-gate (HK/MG) architecture. We report a CPU critical path speed enhancement by implementing a triple gate oxide scheme (so called 28LPG) on HK/MG scheme combined with 20fF/um2 MiM solution for decoupling capacitance. Beside digital speed, we developed a complete RF devices suite enabling high performance analog cells as LNA and VCOs. A 3D integration for high data rate interfaces as wide IOs has been demonstrated based on TSV (Through-Silicon-Via) architecture. Finally ultimate solution for ultra-low power and large memory size is proposed with embedded DRAM offering.
Keywords :
CMOS memory circuits; DRAM chips; capacitance; circuit optimisation; low noise amplifiers; multiprocessing systems; system-on-chip; three-dimensional integrated circuits; voltage-controlled oscillators; 3D integration; CPU critical path speed enhancement; HK-MG scheme; LNA; LP CMOS technology; MiM solution; TSV architecture; VCO; complete RF device; cooptimization methodology; data rate interface; decoupling capacitance; digital speed; embedded DRAM; full-SOC platform; high performance analog cell; high-k metal-gate architecture; memory size; size 28 nm; technology-circuit convergence; through-silicon-via architecture; triple gate oxide scheme; Capacitance; Logic gates; Radio frequency; Random access memory; System-on-a-chip; Through-silicon vias; Transistors;
Conference_Titel :
Electron Devices Meeting (IEDM), 2011 IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
978-1-4577-0506-9
Electronic_ISBN :
0163-1918
DOI :
10.1109/IEDM.2011.6131562
