DocumentCode :
3037670
Title :
First demonstration of ultrathin body c-SiGe channel FDSOI pMOSFETs combined with SiGe(:B) RSD: Drastic improvement of electrostatics (Vth,p tuning, DIBL) and transport (μ0, Isat) properties down to 23nm gate length
Author :
Royer, C. Le ; Villalon, A. ; Cassé, M. ; Cooper, D. ; Mazurier, J. ; Prévitali, B. ; Tabone, C. ; Perreau, P. ; Hartmann, J. -M ; Scheiblin, P. ; Allain, F. ; Andrieu, F. ; Weber, O. ; Batude, P. ; Faynot, O. ; Poiroux, T.
Author_Institution :
LETI, MINATEC, Grenoble, France
fYear :
2011
fDate :
5-7 Dec. 2011
Abstract :
We hereby present for the first time a successful integration of ultrathin (3.2nm) c-Si0.8Ge0.2 layers in Fully Depleted (FD) SOI pMOSFETs (total body thickness: 7.8nm) combined with Si0.7Ge0.3(:B) Raised Source-Drain. Comparisons with SOI devices show that the c-Si0.8Ge0.2/SOI channels enable to tune the threshold voltage by +120mV (with excellent variability performance AVt=1.47mV.μm) without SCE or DIBL degradation (60mV/V @ L=23nm). Moreover c-Si0.8Ge0.2/SOI combined with Si0.7Ge0.3(:B) RSD leads to significant gain in Access resistance (-60%), transconductance and Isat (+170% & +220% @ L=23nm).
Keywords :
Ge-Si alloys; MOSFET; silicon-on-insulator; SOI device; Si0.8Ge0.2; access resistance; c-Si0.8Ge0.2-SOI channel; electrostatics property; gate length; size 23 nm; size 3.2 nm to 7.8 nm; transconductance; ultrathin body c-SiGe channel FDSOI pMOSFET; Logic gates; MOSFETs; Performance evaluation; Silicon; Silicon germanium; Silicon on insulator technology; Strain;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting (IEDM), 2011 IEEE International
Conference_Location :
Washington, DC
ISSN :
0163-1918
Print_ISBN :
978-1-4577-0506-9
Electronic_ISBN :
0163-1918
Type :
conf
DOI :
10.1109/IEDM.2011.6131567
Filename :
6131567
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=3037670
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