DocumentCode :
3037809
Title :
Analysis of Super Cut-off Transistors for Ultralow Power Digital Logic Circuits
Author :
Raychowdhury, Arijit ; Fong, Xuanyao ; Chen, Qikai ; Roy, Kaushik
Author_Institution :
Dept. of Electr. & Comput. Eng., Purdue Univ., IN
fYear :
2006
fDate :
4-6 Oct. 2006
Firstpage :
2
Lastpage :
7
Abstract :
Super cut-off devices with sub-60mV/decade subthreshold swings have recently been demonstrated and being extensively studied. This paper presents a feasibility analysis of such tunneling devices for ultralow power subthreshold logic. Analysis shows that this device can deliver 800times higher performance (@iso-IOFF) compared to a MOSFET. The possible use of this device as a sleep transistor in conjunction with the regular Si MOSFET shows 2000times average improvement in leakage power compared to Si MOSFETs
Keywords :
MOSFET; carbon nanotubes; field effect transistors; logic circuits; low-power electronics; tunnel transistors; MOSFET; carbon nanotube FET; digital logic circuits; sleep transistor; subthreshold logic; subthreshold swings; super cut-off transistors; tunneling devices; tunneling transistors; Digital systems; Logic circuits; Logic design; Logic devices; MOS devices; MOSFET circuits; Power MOSFET; Sleep; Switches; Tunneling; Carbon nanotube FETs; Performance; Tunneling transistors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Low Power Electronics and Design, 2006. ISLPED'06. Proceedings of the 2006 International Symposium on
Conference_Location :
Tegernsee
Print_ISBN :
1-59593-462-6
Type :
conf
DOI :
10.1109/LPE.2006.4271798
Filename :
4271798
Link To Document :
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