Design of a high performance PD SOI for the 0.18 μm technology generation

Author

Sherony, M.J. ; Lo, S.H. ; Schulz, R. ; Leobandung, E. ; Zamdmer, N. ; Sleight, J.W. ; Rausch, W. ; Assaderaghi, F. ; Chen, T.C. ; Shahidi, G.G.

Author_Institution

Semicond. Res. & Dev. Center, IBM Corp., Hopewell Junction, NY, USA

fYear

2000

fDate

2000

Firstpage

197

Lastpage

200

Abstract

This paper presents an optimized partially-depleted SOI device design for the 0.18 μm CMOS technology generation and addresses several SOI unique floating-body effect issues which can affect the design. It is demonstrated that through proper device optimization, these undesired SOI-specific issues can be minimized to improve the manufacturability while maintaining high performance. Inverter delays of 5.1/4.7 ps at 1.5/1.8 V are achieved at low temperature. At room temperature, a delay of 12 ps is achieved at only 0.8 V supply voltage

Keywords

CMOS integrated circuits; circuit optimisation; delays; integrated circuit design; integrated circuit measurement; logic gates; silicon-on-insulator; 1.5 V; 1.8 V; 4.7 ps; 5.1 ps; CMOS technology; PD SOI device design; SOI unique floating-body effect issues; SOI-specific issues; Si-SiO₂; device optimization; inverter delays; manufacturability; optimized partially-depleted SOI device design; supply voltage; technology generation; Degradation; Impact ionization; Intrusion detection; MOS devices; Microelectronics; Notice of Violation; Pulse measurements; Switches; Temperature; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics, 2000. ICM 2000. Proceedings of the 12th International Conference on

Conference_Location

Tehran

Print_ISBN

964-360-057-2

Type

conf

DOI

10.1109/ICM.2000.916443

Filename

916443