Title :
High-performance sub-0.1-/spl mu/m CMOS with low-resistance T-shaped gates fabricated by selective CVD-W
Author :
Hisamoto, D. ; Umeda, K. ; Nakamura, Y. ; Kobayashi, N. ; Kimura, S. ; Nagai, R.
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
Abstract :
This paper describes the high performance of sub-0.1-/spl mu/m T-shaped gate CMOS devices fabricated by using selective W growth. The W growth achieves low-resistance gates smaller than 0.1 /spl mu/m; counter doping achieves threshold voltage scaling, resulting in a ring-oscillator gate-delay time of 21 psec.
Keywords :
CMOS analogue integrated circuits; chemical vapour deposition; integrated circuit metallisation; tungsten; 0.1 micron; 21 ps; CMOS devices; CVD-W; W; counter doping; fabrication; low-resistance T-shaped gates; ring-oscillator gate-delay; selective growth; threshold voltage scaling; Counting circuits; Degradation; Delay effects; Doping; Laboratories; MOS devices; MOSFET circuits; Ring oscillators; Threshold voltage; Time measurement;
Conference_Titel :
VLSI Technology, 1995. Digest of Technical Papers. 1995 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
0-7803-2602-4
DOI :
10.1109/VLSIT.1995.520884
