Title :
Robust Level Converter Design for Sub-threshold Logic
Author :
Chang, Ik Joon ; Kim, Jae-Joon ; Roy, Kaushik
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN
Abstract :
The large supply voltage difference between sub-threshold core logic and I/O makes it extremely challenging to convert signals from core circuit to I/O circuit. In this paper, we propose two novel circuits, clock synchronizer and reduced swing inverter to design dynamic and static level converters for sub-threshold logic. Circuit simulations shows that our level converters work at frequency > 500kHz between 20degC and 40degC with a supply voltage of 0.25V
Keywords :
clocks; logic circuits; logic design; low-power electronics; synchronisation; 0.25 V; 20 to 40 C; I/O circuit; clock synchronizer; core circuit; dynamic level converters; level converter design; reduced swing inverter; static level converters; sub-threshold logic; Clocks; Frequency synchronization; Inverters; Logic circuits; Logic design; Logic devices; Low voltage; MOSFETs; Robustness; Signal design; Design; Sub-threshold logic; level converter; low power circuit design;
Conference_Titel :
Low Power Electronics and Design, 2006. ISLPED'06. Proceedings of the 2006 International Symposium on
Conference_Location :
Tegernsee
Print_ISBN :
1-59593-462-6
DOI :
10.1109/LPE.2006.4271800
