DocumentCode
303793
Title
Performance of the Double-LIB architecture
Author
Bilgen, S. ; Salamah, M.
Author_Institution
Dept. of Electr. & Electron. Eng., Middle East Tech. Univ., Ankara, Turkey
Volume
1
fYear
1996
fDate
13-16 May 1996
Firstpage
166
Abstract
The Double-LIB is an ATM-based switch architecture we have proposed for distributed memory multiprocessor systems. It is essentially a development of the Limited Intermediate Buffer (LIB) idea which was originally proposed to overcome the drawbacks of input and output buffered ATM switches. In this paper, we summarize the characteristics of the Double-LIB and then proceed to report some simulation-based performance results. It is our conclusion that the Double-LIB switch is promising as a solution to the distributed memory multiprocessor communication problem
Keywords
parallel architectures; ATM-based switch architecture; Double-LIB architecture; Limited Intermediate Buffer; distributed memory multiprocessor systems; performance results; Asynchronous transfer mode; Communication switching; Delay; Loss measurement; Message passing; Multiprocessing systems; Scalability; Switches; Throughput; Traffic control;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrotechnical Conference, 1996. MELECON '96., 8th Mediterranean
Conference_Location
Bari
Print_ISBN
0-7803-3109-5
Type
conf
DOI
10.1109/MELCON.1996.550983
Filename
550983
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