Title :
Low frequency noise variability in high-k/metal gate stack 28nm bulk and FD-SOI CMOS transistors
Author :
Ioannidis, E.G. ; Haendler, S. ; Bajolet, A. ; Pahron, T. ; Planes, N. ; Arnaud, F. ; Bianchi, R.A. ; Haond, M. ; Golanski, D. ; Rosa, J. ; Fenouillet-Beranger, C. ; Perreau, P. ; Dimitriadis, C.A. ; Ghibaudo, G.
Author_Institution :
STMicroelectron., Crolles, France
Abstract :
In this paper, we present, for the first time, a thorough investigation of low frequency noise (LFN) and statistical noise variability in high-k/metal gate stack 28nm bulk and FD-SOI CMOS transistors. The experimental results are well interpreted by Monte-Carlo LFN simulations based on the random spatial and energy distribution of discrete traps in the gate dielectric. Our results clearly indicate that the LFN variability of 28nm FD-SOI CMOS technology is improved as compared to previous 45nm and 32nm bulk CMOS technologies.
Keywords :
MOSFET; Monte Carlo methods; high-k dielectric thin films; random processes; semiconductor device noise; silicon-on-insulator; FD-SOI CMOS transistors; LFN variability; Monte Carlo LFN simulations; discrete traps; energy distribution; gate dielectric; high-k-metal gate stack bulk CMOS transistors; low frequency noise variability; random spatial distribution; size 28 nm; statistical noise variability; CMOS integrated circuits; Histograms; Logic gates; MOS devices; Noise; Noise level; Transistors;
Conference_Titel :
Electron Devices Meeting (IEDM), 2011 IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
978-1-4577-0506-9
Electronic_ISBN :
0163-1918
DOI :
10.1109/IEDM.2011.6131581
