DocumentCode
3038074
Title
On routing structure for the hybrid field programmable architecture
Author
Nadjarbashi, Mehran ; Fakhraie, S. Mehdi ; Kaviani, Alireza
Author_Institution
Dept. of Electr. & Comput. Eng., Tehran Univ., Iran
fYear
2000
fDate
2000
Firstpage
259
Lastpage
264
Abstract
In this paper, we investigate the routing architecture for an FPGA with hybrid clusters comprising both look-up tables (LUTs) and PLA-like blocks. We discuss the CAD flow that is used to place and route a number of MCNC benchmark circuits. Our experimental results show the optimized values for cluster-level parameters as well as the best cluster size in terms of area and performance
Keywords
circuit CAD; circuit optimisation; field programmable gate arrays; logic CAD; network routing; table lookup; CAD flow; FPGA; MCNC benchmark circuits; PLA-like blocks; circuit placement; cluster area; cluster performance; cluster size; hybrid clusters; hybrid field programmable architecture; look-up tables; optimized cluster-level parameters; routing architecture; routing structure; Computer architecture; Digital circuits; Field programmable gate arrays; Logic circuits; Logic devices; Programmable logic arrays; Programmable logic devices; Routing; Switches; Table lookup;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronics, 2000. ICM 2000. Proceedings of the 12th International Conference on
Conference_Location
Tehran
Print_ISBN
964-360-057-2
Type
conf
DOI
10.1109/ICM.2000.916456
Filename
916456
Link To Document