DocumentCode
3038098
Title
An efficient CPLD technology mapping under the time constraint
Author
Kim, Hi-Seok ; Kim, Jae-Jin ; Lin, Chi-Ho
Author_Institution
Dept. of Electron. Eng., Chongju Univ., South Korea
fYear
2000
fDate
2000
Firstpage
265
Lastpage
268
Abstract
In this paper, we proposed a new technology mapping algorithm for CPLD under a time constraint (TMCPLD). In our technology mapping algorithm, a given Boolean network generated a feasible cluster. The generated feasible cluster creates clusters with minimum area under the time constraint. A covered Boolean network is transformed to a Boolean equation. The transformed equations are reconstructed in order to fit the architecture of a selected target CPLD using collapsing and bin-packing. To demonstrate the efficiency of our approach, we applied our algorithm to MCNC benchmarks and compared the results with those of the existing algorithms. The experimental results show that our approach is better than any of the existing algorithms in the number of logic blocks
Keywords
Boolean functions; bin packing; integrated circuit design; logic design; programmable logic devices; Boolean equation; Boolean network; CPLD; CPLD technology mapping; MCNC benchmarks; TMCPLD technology mapping algorithm; bin-packing; collapsing; covered Boolean network; feasible cluster generation; logic blocks; minimum area clusters; target CPLD architecture; technology mapping algorithm; time constraint; transformed equation reconstruction; Circuit synthesis; Clustering algorithms; Combinational circuits; Computer science; Digital circuits; Equations; Field programmable gate arrays; Logic circuits; Logic functions; Time factors;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronics, 2000. ICM 2000. Proceedings of the 12th International Conference on
Conference_Location
Tehran
Print_ISBN
964-360-057-2
Type
conf
DOI
10.1109/ICM.2000.916457
Filename
916457
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