Title :
On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs
Author :
Shianling Wu ; Laung-Terng Wang ; Zhigang Jiang ; Jiayong Song ; Boryau Sheu ; Xiaoqing Wen ; Hsiao, Michael S. ; Li, James Chien-Mo ; Jiun-Lang Huang ; Apte, R.
Author_Institution :
SynTest Technol. Inc., Sunnyvale, CA
Abstract :
This paper presents a hybrid automatic test pattern generation (ATPG) technique using the staggered single-capture scheme followed by the one-hot single-capture scheme for detecting structural faults, which are neither timing-dependent nor sequence-dependent in a scan design. Structural faults are also called combinational faults or DC faults, such as stuck-at faults and bridging faults. Typically, the one-hot scheme achieves near maximum fault coverage, takes shorter ATPG run time, but produces a large pattern count, whereas the staggered scheme produces smaller pattern count but needs long ATPG run time and may suffer from some fault coverage loss. The proposed hybrid technique is intended to optimize fault coverage with respect to the one-hot scheme by exploring trade-offs between pattern count and ATPG run time of multimillion-gate scan designs. Experimental results show that the proposed hybrid technique can achieve higher fault coverage and up to 4X smaller pattern count than the one-hot scheme.
Keywords :
automatic test pattern generation; design for testability; fault diagnosis; ATPG run time; DC fault; combinational fault; fault coverage; hybrid automatic test pattern generation technique; hybrid single-capture; pattern count; structural fault detection; testing scan design; Automatic test pattern generation; Circuit faults; Circuit testing; Clocks; Design for testability; Design optimization; Sequential analysis; Sequential circuits; Test pattern generators; USA Councils; Automatic Test Pattern Generation; Hybrid Single-Capture; One-Hot Single-Capture; Scan Testing; Simultaneous Single-Capture; Staggered Single-Capture;
Conference_Titel :
Defect and Fault Tolerance of VLSI Systems, 2008. DFTVS '08. IEEE International Symposium on
Conference_Location :
Boston, MA
Print_ISBN :
978-0-7695-3365-0
DOI :
10.1109/DFT.2008.29