A Fault Tolerance Aware Synthesis Methodology for Threshold Logic Gate Networks

Threshold logic technology is conceived as the crucial alternate emerging technology to CMOS implementation in nanoelectronic era. The gate that is implemented with threshold logic is called a threshold logic gate (TLG). Threshold gates are very fast and implement complex functionalities thus reducing the logic levels in the circuit implementation. Extensive research has been done in the development of suitable synthesis methodologies in the past, predominantly greedy. In this work, a synthesis methodology is proposed for increased fault tolerance. Experimental results demonstrate the effectiveness of the proposed method both in terms of resulting TLG count in the network implementation and reliability.