DocumentCode :
3038267
Title :
An 8 b 650 MHz folding ADC
Author :
van Valburg, J. ; van de Plassche, R.
Author_Institution :
Phillips Res. Lab., Eindhoven, Netherlands
fYear :
1992
fDate :
19-21 Feb. 1992
Firstpage :
30
Lastpage :
31
Abstract :
Where a flash analog-to-digital converter (ADC) needs 2/sup N/-1 comparators to convert an analog value into an N-bit binary code, an M-times folding ADC can perform this function needing slightly more than 2/sup N//M comparators. In the design reported, N=8 and the folding factor M=8. Reduction in the number of comparators is obtained by analog preprocessing of the ADC input signal. In the design considered, power consumption, chip area, and parasitic capacitance at the analog input of the ADC are reduced by using only four folding blocks and 8-times interpolation.<>
Keywords :
analogue-digital conversion; monolithic integrated circuits; 650 MHz; 8 bit resolution; A/D convertor; comparators; folding ADC; interpolation; Binary codes; Circuits; Data preprocessing; Error correction; Frequency; Interpolation; Laboratories; Resistors; Signal processing; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 1992. Digest of Technical Papers. 39th ISSCC, 1992 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0573-6
Type :
conf
DOI :
10.1109/ISSCC.1992.200395
Filename :
200395
Link To Document :
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