Title :
A 10 b 50 MS/s pipelined ADC
Author :
Vorenkamp, P. ; Verdaasdonk, J.P.M.
Author_Institution :
Philips Res. Lab., Eindhoven, Netherlands
Abstract :
Most multistep analog-to-digital converter (ADC) architectures presented thus far suffer from poor linearity caused by the sample and hold as well as the internal digital-to-analog converter (DAC). Furthermore, the gain-matching between coarse and fine ADC gives rise to nonmonotonicity. A fully differential two-step ADC is described which presents solutions for sample and hold, the DAC, the gain-matching between coarse and fine high performance with low power consumption and small chip area.<>
Keywords :
analogue-digital conversion; monolithic integrated circuits; pipeline processing; fully differential two-step ADC; gain-matching; low power consumption; multistep A/D convertor; pipelined ADC; Broadband amplifiers; Circuits; Differential amplifiers; Diodes; Energy consumption; Latches; Linearity; Switches; Tail; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 1992. Digest of Technical Papers. 39th ISSCC, 1992 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0573-6
DOI :
10.1109/ISSCC.1992.200396
