DocumentCode :
3038430
Title :
Thermal Via Allocation for 3D ICs Considering Temporally and Spatially Variant Thermal Power
Author :
Yu, Hao ; Shi, Yiyu ; He, Lel ; Karnik, Tanay
Author_Institution :
Dept. of Electr. Eng., California Univ., Los Angeles, CA
fYear :
2006
fDate :
4-6 Oct. 2006
Firstpage :
156
Lastpage :
161
Abstract :
All existing methods for thermal-via allocation are based on a steady-state thermal analysis and may lead to excessive number of thermal vias. This paper develops an accurate and efficient thermal-via allocation considering temporally and spatially variant thermal-power. The transient temperature is calculated using macromodel by a structured and parameterized model reduction, which generates temperature sensitivity with respect to thermal-via density. By defining a thermal-violation integral based on the transient temperature, a nonlinear optimization problem is formulated to allocate thermal-vias and minimize thermal violation integral. This optimization problem is transformed into a sequence of subproblems by Lagrangian relaxation, and each subproblem is solved by quadratic programming using sensitives from the macromodel. Experiments show that compared to the existing method using steady-state thermal analysis, our method is 126times faster to obtain the temperature profile, and reduces the number of thermal vias by 2.04times under the same temperature bound
Keywords :
circuit optimisation; integrated circuit design; integrated circuit modelling; quadratic programming; thermal analysis; thermal management (packaging); 3D integrated circuits; Lagrangian relaxation; nonlinear optimization problem; parameterized model reduction; quadratic programming; steady-state thermal analysis; structured model reduction; temperature sensitivity; thermal power; thermal via allocation; thermal-via density; thermal-violation integral; transient temperature; Dielectric substrates; Lagrangian functions; Quadratic programming; Reduced order systems; Steady-state; Temperature sensors; Thermal conductivity; Thermal engineering; Thermal resistance; Three-dimensional integrated circuits; Algorithms; Design; Model Order Reduction; SQP Optimization; Thermal Management and Simulation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Low Power Electronics and Design, 2006. ISLPED'06. Proceedings of the 2006 International Symposium on
Conference_Location :
Tegernsee
Print_ISBN :
1-59593-462-6
Type :
conf
DOI :
10.1109/LPE.2006.4271828
Filename :
4271828
Link To Document :
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