Minimization of CTS of k-CNOT Circuits for SSF and MSF Model

Author

Ibrahim, Muhammad ; Chowdhury, Ahsan Raja ; Babu, Hafiz Md Hasan

Author_Institution

Dept. of Comput. Sci. & Eng., Univ. of Dhaka, Dhaka

fYear

2008

fDate

1-3 Oct. 2008

Firstpage

290

Lastpage

298

Abstract

In this paper, we consider the problem of testing reversible circuits for a particular fault model: Stuck-at Fault Model. We propose a design-for-test construction technique for k-CNOT circuit having k ges 1 and only 2 test vector (i.e. minimal) suffice as their complete test set. We have also shown the way to exploit our method for the case of 0-CNOT circuits. Finally we provide some experimental results for the proposed method and compare it with existing method to show how the proposed one outperforms the existing one both in terms of number of test vectors of complete test set and number of gates need to be replaced in the design-for-test.

Keywords

design for testability; fault simulation; logic testing; CTS; MSF model; SSF model; complete test set; design-for-test construction technique; k-CNOT circuits; reversible circuits; stuck-at fault model; test vector; Circuit faults; Circuit testing; DH-HEMTs; Design for testability; Electrical fault detection; Fault detection; Minimization; Production; Temperature; Wires; Design for Test; Stuck-at-Fault; Test Vector;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance of VLSI Systems, 2008. DFTVS '08. IEEE International Symposium on

Conference_Location

Boston, MA

ISSN

1550-5774

Print_ISBN

978-0-7695-3365-0

Type

conf

DOI

10.1109/DFT.2008.38

Filename

4641184