DocumentCode
3038457
Title
A PLL clock generator with 5 to 110 MHz lock range for microprocessors
Author
Young, I.A. ; Greason, J.K. ; Smith, J.E. ; Wong, K.L.
Author_Institution
Intel Corp., Portland, OR, USA
fYear
1992
fDate
19-21 Feb. 1992
Firstpage
50
Lastpage
51
Abstract
The authors describe a phase-locked-loop (PLL)-based deskewed clock generator that is fully integrated with a microprocessor and achieves a skew of less than 0.1 ns with peak-to-peak jitter of 0.45 ns using an 0.8- mu m CMOS technology. The block diagram of the deskewed clock generator is shown along with the measured schmoo diagram of the PLL clock generator functionality frequency versus supply voltage.<>
Keywords
CMOS integrated circuits; clocks; microprocessor chips; mixed analogue-digital integrated circuits; phase-locked loops; timing circuits; 0.8 micron; 5 to 110 MHz; CMOS technology; PLL clock generator; microprocessors; phase-locked-loop; Clocks; Dynamic range; Jitter; Microprocessors; Moon; Phase locked loops; Resistors; Testing; Voltage; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1992. Digest of Technical Papers. 39th ISSCC, 1992 IEEE International
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-7803-0573-6
Type
conf
DOI
10.1109/ISSCC.1992.200405
Filename
200405
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