Electrical evaluation of 130-nm MOSFETs with TSV proximity in 3D-SIC structure

Author

Yang, Yu ; Katti, Guruprasad ; Labie, Riet ; Travaly, Youssef ; Verlinden, Bert ; De Wolf, Ingrid

Author_Institution

IMEC vzw, Leuven, Belgium

fYear

2010

fDate

6-9 June 2010

Firstpage

1

Lastpage

3

Abstract

Through-silicon via (TSV) proximity is electrically evaluated for the first time based on a 130-nm CMOS platform. Transistors with TSVs in a two die stacking structure were successfully designed, fabricated and tested. With a minimum distance of 1.1 μm from a 5.2 μm diameter TSV, both PMOS and NMOS showed normal functionality. No performance degradation was identified compared to control cases without TSVs. The stability of this structure was investigated by thermal cycling tests. Measurements after 1000 cycles between -55 and 125°C demonstrated good robustness of the stacked integrated circuit (SIC) structure. Residual stress induced by the TSVs was experimentally examined by micro-Raman spectroscopy. The results revealed that TSV induced stress is negligible for carrier mobility in this technology.

Keywords

CMOS integrated circuits; MOSFET; Raman spectroscopy; 3D-SIC structure; CMOS platform; MOSFET; NMOS; PMOS; carrier mobility; micro-Raman spectroscopy; size 1.1 mum; size 130 nm; size 5.2 mum; stacked integrated circuit structure; temperature -55 degC; temperature 125 degC; through-silicon via proximity; Circuit stability; Circuit testing; Integrated circuit measurements; MOS devices; MOSFETs; Residual stresses; Stacking; Thermal degradation; Thermal stability; Through-silicon vias;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference (IITC), 2010 International

Conference_Location

Burlingame, CA

Print_ISBN

978-1-4244-7676-3

Type

conf

DOI

10.1109/IITC.2010.5510710

Filename

5510710