Built in self test for ring addressed FIFOs with transparent latches

Author

Fenstermaker, Larry ; Kim, Ilyoung ; Lewandowski, Jim ; Nagy, Jeffrey J.

Author_Institution

Lucent Technol., Bell Labs., USA

fYear

1999

fDate

1999

Firstpage

72

Lastpage

77

Abstract

The use of special purpose complex embedded memories is becoming increasingly common. Their complex functionality, large sizes, decreasing feature sizes, and limited controllability/observability combine to make testing ever more difficult. In this paper, we describe a built in self test (BIST) method for testing ring addressed first in first out memories (FIFOs) that use transparent input latches for applications that require high data rates. The method used is compared to previous results for ring addressed FIFOs with edge triggered input latches. Several different special test modes are used to provide both more efficient and more complete BIST

Keywords

application specific integrated circuits; built-in self test; embedded systems; integrated circuit testing; integrated memory circuits; built in self test; controllability; data rates; edge triggered input latches; feature sizes; first in first out memories; functionality; observability; ring addressed FIFOs; special purpose complex embedded memories; test modes; transparent input latches; Automatic testing; Built-in self-test; Clocks; Delay; Information retrieval; Pipelines; Propagation losses; Protection; Read-write memory; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Memory Technology, Design and Testing, 1999. Records of the 1999 IEEE International Workshop on

Conference_Location

San Jose, CA

ISSN

1087-4852

Print_ISBN

0-7695-0259-8

Type

conf

DOI

10.1109/MTDT.1999.782686

Filename

782686