DocumentCode :
3038652
Title :
Porous low k structural design to meet next generation interconnect needs
Author :
Matz, Marua ; Haas, Mary K. ; Vrtis, Raymond N. ; Jiang, Xuezhong ; Wu, Aiping ; Rao, Madhukar B. ; O´Neil, Mark L.
Author_Institution :
Electron. Technol. Div., Air Products & Chem. Inc., Allentown, PA, USA
fYear :
2010
fDate :
6-9 June 2010
Firstpage :
1
Lastpage :
3
Abstract :
As porous low k films are integrated for 45nm/32nm and extend into 22nm/16nm technology nodes, there is a need for more rigorous structural design of porous low k films to meet the integration challenges. This paper demonstrates the ability to tune porous low k films and discusses the impact of these choices to subsequent integration steps such as etch, ash and wet clean processes. Balancing carbon content in the film to minimize damage needs to be coupled with improving mechanical properties for packaging compatibility. By tuning the porous low k deposition process, these properties can be balanced.
Keywords :
etching; integrated circuit interconnections; low-k dielectric thin films; porous semiconductors; ash process; carbon content; etch process; next generation interconnect; porous low k film; porous low k structural design; wet clean process; Bonding; Capacitance; Chemical products; Chemical technology; Glass; Mechanical factors; Packaging; Plasma applications; Plasma chemistry; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Interconnect Technology Conference (IITC), 2010 International
Conference_Location :
Burlingame, CA
Print_ISBN :
978-1-4244-7676-3
Type :
conf
DOI :
10.1109/IITC.2010.5510727
Filename :
5510727
Link To Document :
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