Title :
A Case Study of ATPG Delay Path Performance Based on Measured Power Rail Integrity
Author :
Abuhamdeh, Z. ; Hannagan, R.
Author_Institution :
TranSwitch Corp., Shelton, CT
Abstract :
Summary form only given. It is a well known problem that power rail integrity can affect the performance of a chip. This degradation of performance can produce failures in extreme chips built closer to worst case (WC) process and operated under slowest environmental conditions. ATPG delay path can be used to measure the performance of the most vulnerable delay paths of the chip in a production environment and operate as an affective screen for such collective defects in performance and power rail integrity.
Keywords :
automatic test pattern generation; integrated circuit testing; microprocessor chips; ATPG delay path performance; automatic test pattern generation; environmental conditions; extreme chips; power rail integrity; production environment; worst case process; Automatic test pattern generation; Degradation; Delay; Fault tolerant systems; Instruments; Optical wavelength conversion; Power measurement; Production; Rails; Semiconductor device measurement;
Conference_Titel :
Defect and Fault Tolerance of VLSI Systems, 2008. DFTVS '08. IEEE International Symposium on
Conference_Location :
Boston, MA
Print_ISBN :
978-0-7695-3365-0
DOI :
10.1109/DFT.2008.69
