Integration and frequency dependent electrical modeling of Through Silicon Vias (TSV) for high density 3DICs

Author

Cadix, L. ; Rousseau, M. ; Fuchs, C. ; Leduc, P. ; Thuaire, A. ; El Farhane, R. ; Chaabouni, H. ; Anciant, R. ; Huguenin, J.-L. ; Coudrain, P. ; Farcy, A. ; Bermond, C. ; Sillon, N. ; Fléchet, B. ; Ancey, P.

Author_Institution

STMicroelectronics, Crolles, France

fYear

2010

fDate

6-9 June 2010

Firstpage

1

Lastpage

3

Abstract

Evaluation of Through Silicon Via (TSV) electrical parameters is mandatory to improve heterogeneous 3D chip performance in the frame of a “more than Moore” roadmap. Accurate modeling of TSV is consequently essential to perform design, material and process optimizations. This paper presents a frequency dependent analytical model including MOS effect of high aspect ratio TSV achieved in a full CMOS 65 nm platform according to a face-to-face Via Last process. Specific test structures with bulk contacts to polarize silicon were integrated enabling C(V) and RF measurements. TSV equivalent model including all substrate effects is proposed and simplified according to CMOS 65 nm specificities (voltage, frequency, dimensions and Si conductivity) leading to a full analytical model.

Keywords

CMOS integrated circuits; three-dimensional integrated circuits; MOS effect; RF measurements; TSV equivalent model; bulk contacts; electrical parameters; frequency dependent electrical modeling; full CMOS platform; high density 3D IC; process optimizations; size 65 nm; specific test structures; through silicon vias; Analytical models; CMOS process; Design optimization; Frequency dependence; Polarization; Process design; Semiconductor device modeling; Silicon; Testing; Through-silicon vias;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference (IITC), 2010 International

Conference_Location

Burlingame, CA

Print_ISBN

978-1-4244-7676-3

Type

conf

DOI

10.1109/IITC.2010.5510728

Filename

5510728