A comparative simulation study of four multilevel DRAMs

Author

Birk, Gershom ; Elliott, Duncan G. ; Cockburn, Bruce F.

Author_Institution

Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta., Canada

fYear

1999

fDate

1999

Firstpage

102

Lastpage

109

Abstract

Multilevel DRAM (MLDRAM) attempts to increase storage density by recording more than one bit per cell. Several different two-bit-per-cell schemes have been described in the literature; however it is difficult to compare them directly because the original papers use different technologies and operating conditions. This paper presents a detailed simulation study that compares three published MLDRAM schemes, along with a new MLDRAM scheme that combines the speed of a MLDRAM proposed by Furuyama et al. (1989) and the noise cancellation techniques of a MLDRAM proposed by Gillingham (1996). Our SPICE simulation models use the same array size and process models for each to allow us to make direct comparisons

Keywords

CMOS memory circuits; DRAM chips; SPICE; circuit simulation; integrated circuit modelling; integrated circuit noise; CMOS process; MLDRAM schemes; SPICE simulation models; array size; comparative simulation study; multilevel DRAMs; noise cancellation techniques; process models; storage density; two-bit-per-cell schemes; Capacitance; Capacitors; Circuits; Computational modeling; Data mining; Random access memory; Switches; Variable structure systems; Voltage; World Wide Web;

fLanguage

English

Publisher

ieee

Conference_Titel

Memory Technology, Design and Testing, 1999. Records of the 1999 IEEE International Workshop on

Conference_Location

San Jose, CA

ISSN

1087-4852

Print_ISBN

0-7695-0259-8

Type

conf

DOI

10.1109/MTDT.1999.782690

Filename

782690