MOS decision and clock-recovery circuits for Gb/s optical-fiber receivers

Low-cost interface electronics are key for wider acceptance of 1-GHz optical-fiber data links for local area networks. ICs for the transmitter and receiver functions have been developed in GaAs and high-speed silicon bipolar technologies, but the prospect of implementing the requisite functions as MOS ICs has so far remained unfulfilled. Circuit designs for on-chip clock recovery and data regeneration at low error rates pose the greatest challenges. The authors report the first integrated versions of these elements exceeding 1 Gb/s operation fabricated in a 1- mu m nMOS technology. Fully differential and quasi-complimentary circuits are used for immunity from on-chip high-frequency noise. All clock phases are generated on-chip, requiring a single clock and complementary data inputs.<>