Low-power SRAM circuit design

This paper presents an extensive summary of the latest developments in low-power circuit techniques and methods for Static Random Access Memories. The key techniques in power reduction in both active and standby modes are: capacitance reduction by using divided word-line structure or single-bitline cross-point cell activation, pulse operation by using ATD generator and reduced signal swings on high-capacitance predecode lines, write bus lines and datalines, AC current reduction by using multistage decoding, operating voltage reduction coupled with low-power sensing by using charge-transfer amplification, step-down boosted word-line scheme or full current-mode read/write operation and leakage current suppression by using dual-Vt, Auto-Backgate-Controlled multiple-Vt, or dynamic leakage cut-off techniques