A Si bipolar chip set for 10 Gb/s optical receiver

Author

Soda, M. ; Suzaki, T. ; Morikawa, T. ; Tezuka, H. ; Ogawa, C. ; Fujita, S. ; Takemura, Hiroshi ; Tashiro, T.

Author_Institution

NEC Corp., Kawasaki, Japan

fYear

1992

fDate

19-21 Feb. 1992

Firstpage

100

Lastpage

101

Abstract

The development of a chip set comprised of analog circuits with a bandwidth exceeding 10 GHz and digital circuits operating at 10 Gb/s are required for a 10-Gb/s direct-detection optical receiver. The best performance to date using Si bipolar technology is a 10-GHz bandwidth preamplifier or a 3.6-GHz bandwidth gain-controllable amplifier. A preamplifier and gain-controllable amplifier with a bandwidth exceeding 10 GHz, and decision circuits operating at 10 Gb/s are achieved by optimized high-speed silicon bipolar circuit blocks, including a dual feedback loop, peaking circuit, and impedance matched buffer to achieve a 11.2-GHz bandwidth with 53-dB Omega transimpedance gain. The gain-controllable amplifier uses a current-dividing gain-control and emitter peaking circuit and has 11.4-GHz bandwidth with 20-dB variable gain.<>

Keywords

automatic gain control; bipolar integrated circuits; elemental semiconductors; optical receivers; preamplifiers; silicon; 10 Gbit/s; 11.2 GHz; 20 dB; Si; analog circuits; bipolar chip set; decision circuits; direct-detection optical receiver; dual feedback loop; gain-controllable amplifier; impedance matched buffer; optical receiver; peaking circuit; preamplifier; transimpedance gain; Analog circuits; Bandwidth; Digital circuits; Feedback circuits; Feedback loop; Impedance; Optical amplifiers; Optical receivers; Preamplifiers; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1992. Digest of Technical Papers. 39th ISSCC, 1992 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-0573-6

Type

conf

DOI

10.1109/ISSCC.1992.200431

Filename

200431