DocumentCode
3038813
Title
A 100 MHz macropipelined CISC CMOS microprocessor
Author
Badeau, R. ; Bahar, R.I. ; Bernstein, D. ; Biro, L. ; Bowhill, W. ; Brown, J. ; Case, M. ; Castelino, R. ; Cooper, E. ; Delaney, M. ; Deverell, D. ; Edmondson, J. ; Ellis, J. ; Fischer, T. ; Fox, T. ; Gowan, M. ; Gronowski, P. ; Herrick, W. ; Jain, A. ; M
Author_Institution
Digital Equipment Corp., Hudson, MA, USA
fYear
1992
fDate
19-21 Feb. 1992
Firstpage
104
Lastpage
105
Abstract
A macropipelined CISC microprocessor implemented in a 0.75- mu m CMOS 3.3-V three-metal-layer technology is described. The 1.3 M-transistor custom chip measures 1.62*1.46 cm/sup 2/, dissipates 18 W (peak), and is packaged in a 339-pin PGA. The chip implements a macroinstruction pipeline to execute the instruction set of a popular CISC minicomputer. A block diagram of the major functional units is shown along with die micrograph.<>
Keywords
microprocessor chips; parallel architectures; pipeline processing; 0.75 micron; 18 W; 3.3 V; PGA; custom chip; die micrograph; instruction set; macropipelined CISC CMOS microprocessor; three-metal-layer technology; CMOS technology; Clocks; Decoding; Delay; Flip-flops; Microprocessors; Read only memory; Routing; Semiconductor device measurement; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1992. Digest of Technical Papers. 39th ISSCC, 1992 IEEE International
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-7803-0573-6
Type
conf
DOI
10.1109/ISSCC.1992.200433
Filename
200433
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