Title :
A 1000 MIPS BiCMOS microprocessor with superscalar architecture
Author :
Nishii, O. ; Hanawa, M. ; Nishimukai, T. ; Suzuki, M. ; Yano, K. ; Hiraki, M. ; Shukuri, S. ; Nishida, T.
Author_Institution :
Hitachi Central Res. Lab., Tokyo, Japan
Abstract :
A 1000 MIPS computer, integrated on a single chip and experimentally developed using 0.3- mu m self-aligned BiCMOS technology, is described. It features superscalar processing and pipelined access of interleaved secondary cache. The authors describe circuit techniques of the cache, TLB, register, file, and ALU (arithmetic and logic unit) operating at 250 MHz.<>
Keywords :
BiCMOS integrated circuits; microprocessor chips; parallel architectures; pipeline processing; 0.3 micron; 1000 MIPS; 250 MHz; ALU; BiCMOS microprocessor; TLBs; buffer storage; circuit techniques; interleaved secondary cache; pipelined access; self-aligned technology; superscalar architecture; Adders; BiCMOS integrated circuits; Clocks; Decoding; Delay; Logic; Microprocessors; Pipelines; Registers; Sliding mode control;
Conference_Titel :
Solid-State Circuits Conference, 1992. Digest of Technical Papers. 39th ISSCC, 1992 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0573-6
DOI :
10.1109/ISSCC.1992.200438
