Path-finding for integration of porous SiOCH films (k∼2.5) in system-LSIs

Impacts of k-value reduction on LSI performances are clarified quantitatively using 2M-gate net-list. Reduction in k-value from 3.0 to 2.5 for M2-M5 interconnect layers achieves 11%-drop in interconnect parasitic capacitance (C_int) and 8.4%-reduction in propagation delay (τ_d), which also shrinks the effective variability of τ_d to improve LSI operation margins. From a viewpoint of BEOL fabrication with k~2.5, a carbon-rich porous SiOCH film has high tolerance to process-induced damages, resulting in lower C_int than that of an O-rich film with similar k-value. Sustainability to FCBGA packaging with Pb-free solder bumps is also confirmed for the multi-level interconnects with the C-rich porous SiOCH.