Title :
3D large scale integration technology using Wafer-on-Wafer (WOW) stacking
Author_Institution :
Univ. of Tokyo, Tokyo, Japan
Abstract :
Wafer-scale three-dimensional (3D) technologies, so-called Wafer-on-Wafer (WOW), beyond post-scaling for high-density integration are discussed. WOW module technologies consisting of wafer thinning, stacking, TSV (Through-Silicon-Via) interconnects, and packaging are described. No degradation for advanced 35-nm SRAM logic and FRAM devices was observed with ultra-thinning below 10-μm for 300-mm and 200-mm wafers. Production-worthy die yield due to wafer stacking and a comparison of critical scaling for future manufacturability are presented.
Keywords :
SRAM chips; integrated circuit interconnections; integrated circuit packaging; logic circuits; three-dimensional integrated circuits; 3D large scale integration technology; FRAM devices; SRAM logic devices; integrated circuit packaging; size 200 mm; size 300 mm; size 35 nm; through-silicon-via interconnects; wafer thinning; wafer-on-wafer stacking; wafer-scale three-dimensional technology; Degradation; Ferroelectric films; Large scale integration; Logic devices; Manufacturing; Nonvolatile memory; Packaging; Random access memory; Stacking; Through-silicon vias;
Conference_Titel :
Interconnect Technology Conference (IITC), 2010 International
Conference_Location :
Burlingame, CA
Print_ISBN :
978-1-4244-7676-3
DOI :
10.1109/IITC.2010.5510747
