Dual ferroelectric capacitor architecture and its application to TAG RAM

Transistor scaling has enabled more memory to be embedded on-chip to accelerate large scale applications. However, increased leakage current in scaled technologies resulted in higher standby power consumption in volatile memories. Nonvolatile memories have been researched and developed as solutions to these problems. However, non-volatile memories such as Flash or magnetic spin torque memories require large drive currents. On the other hand, ferroelectric capacitors take advantage of non-linear capacitance to store data and are compatible with CMOS fabrication process. Furthermore, dual ferroelectric capacitor (DFeCAP) architecture was developed to implement low-power logic/memory functional units. This paper evaluates a TAG RAM implementation based on DFeCAP architecture using a generic, HSPICE compatible ferroelectric capacitor model. The paper also discusses the impact of parametric process variations on the performance of DFeCAP cell and proposes design methodologies to achieve variation-tolerance. Our simulations demonstrate that compared to 130 nm CMOS implementation, the ferroelectric memory architecture is 97% better in terms of power and 37% better in terms of area.