High-speed links for memory interface

Author

Sim, Jae-Yoon ; Lee, Seon-Kyoo ; Kim, Young-Sik ; Sohn, Young-Soo ; Choi, Joo Sun

Author_Institution

Pohang Univ. of Sci. & Technol. (POSTECH), Pohang, South Korea

fYear

2010

fDate

2-4 June 2010

Firstpage

16

Lastpage

19

Abstract

Memory, as a fundamental component of a system, has been a leading drive for high-speed parallel links, and it requires interface technology providing stable data rate of multi-Gb/s/pin. The highest data rate in memory IO, presented by GDDR5, shows the data rate of up to 6Gb/s/pin with the traditional single-ended signaling on PCB. Further step to higher throughput, however, presents critical problems which must be overcome by taking challenges in packaging, process as well as circuit design. This paper reviews current status of memory interface circuits and introduces several promising interface technologies such as TSV, Wide-IO, inductive coupling, and multiple serial links.

Keywords

semiconductor storage; GDDR5; PCB; circuit design; high-speed links; high-speed parallel links; interface technology; memory IO; memory interface circuits; single-ended signaling; Circuit synthesis; Coupling circuits; Driver circuits; Packaging; Random access memory; Resistors; Sun; Through-silicon vias; Throughput; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

IC Design and Technology (ICICDT), 2010 IEEE International Conference on

Conference_Location

Grenoble

Print_ISBN

978-1-4244-5773-1

Type

conf

DOI

10.1109/ICICDT.2010.5510752

Filename

5510752