Title :
An analog neural network processor for self-organizing mapping
Author :
Sheu, B.J. ; Choi, J. ; Chang, C.-F.
Author_Institution :
Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
Abstract :
The building blocks of a self-organizing analog neural chip are shown. Its function is to evaluate the large number of dot products of the given input vectors and the stored weight vectors in a fully parallel format. Lateral competition is to be performed among the analog output voltages and the neural unit with the largest voltage level is to emerge as a single winner. Updating synapse weights is performed in a digital signal processor using an unsupervised learning rule. Design considerations addressed in the construction of the WTA (winner-take-all) circuit are: high resolution, fast operation, and layout compactness. The 4-MHz analog neural network processor chip, fabricated in a 2- mu m CMOS process, contains 25 neurons in the input layer and 64 neurons in the competitive layer. The behavior of the WTA circuit with only one winner for a lossy image data compression application is shown.<>
Keywords :
CMOS integrated circuits; analogue processing circuits; image coding; learning (artificial intelligence); self-organising feature maps; CMOS; WTA; analog neural network processor; competitive layer; dot products; fully parallel format; input vectors; layout compactness; lossy image data compression; self-organizing mapping; stored weight vectors; synapse weights; unsupervised learning rule; CMOS process; Circuits; Data compression; Digital signal processors; Neural network hardware; Neural networks; Neurons; Signal resolution; Unsupervised learning; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 1992. Digest of Technical Papers. 39th ISSCC, 1992 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0573-6
DOI :
10.1109/ISSCC.1992.200449
