Investigation of failures on dual-dies stacked package

The exploration for higher performance in memory has steered the industry towards dual-dies architectures which has significantly increased the challenges in silicon-package integration. In dual-dies package (DDP) technology is recommended to pack two semiconductor chips within one single package module. In our dual-die package use of a back-to-back die stacked configurations with two high-capacity DRAM chips in one single package module to enhance the performance of DRAM devices. During reliability qualification, suffered abnormalities occurrence and we conducted failures analyses and studied failure root causes. From investigation results, both failure analyses and generation mechanism are reported.