A novel atomic layer oxidation technique for EOT scaling in gate-last high-к/metal gate CMOS technology

We demonstrated sub-1nm equivalent oxide thickness (EOT) for a gate-last high-k/metal scheme. This is enabled by (1) controllable 1000°C high temperature atomic layer oxidation on a chemical oxide (chemox) to form <; 0.5 nm high quality SiO₂ interfacial layer (IL); (2) nitrogen profile optimization on post high- k nitridation and anneal. Competitive gate leakage and mobility are achieved at the scaled EOT compared to a chemox IL control (0.2 nm thinner). The physical properties of the gate stack are studied by XPS and SIMS analysis.