Title :
A 100 MHz 4 Mb cache DRAM with fast copy-back scheme
Author :
Dosaka, K. ; Konishi, Y. ; Hayano, K. ; Himukashi, K. ; Yamazaki, A. ; Hart, C.A. ; Kumanoya, M. ; Hamano, H. ; Yoshihara, T.
Author_Institution :
Mitsubishi Electric Corp., Itami, Japan
Abstract :
A 4-Mb cache DRAM (CDRAM) which integrates 16-kb SRAM as a cache memory and 4-Mb DRAM is described. The 4-Mb CDRAM features 100-MHz cache hit operation with an improved localized cache architecture. Circuits require only 7% more area than a conventional 4-Mb DRAM. There is 3* faster cache miss access over conventional copy back with fast copy back, as well as maximized mapping flexibility (applicable to direct mapping, set-associative, and full-associative). The block diagram of the 4-Mb CDRAM is shown along with a micrograph.<>
Keywords :
DRAM chips; buffer storage; memory architecture; 100 MHz; 4 Mbit; CDRAM; cache DRAM; cache hit operation; cache miss access; fast copy-back scheme; localized cache architecture; mapping flexibility; Cache memory; Central Processing Unit; Clocks; Computer hacking; Delay effects; Flexible printed circuits; Pins; Random access memory; Registers; Size control;
Conference_Titel :
Solid-State Circuits Conference, 1992. Digest of Technical Papers. 39th ISSCC, 1992 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0573-6
DOI :
10.1109/ISSCC.1992.200455
