Dual-channel technology with cap-free single metal gate for high performance CMOS in gate-first and gate-last integration

Author

Witters, L. ; Mitard, J. ; Veloso, A. ; Hikavyy, A. ; Franco, J. ; Kauerauf, T. ; Cho, M. ; Schram, T. ; Sebai, F. ; Yamaguchi, S. ; Takeoka, S. ; Fukuda, M. ; Wang, W.-E. ; Duriez, B. ; Eneman, G. ; Loo, R. ; Kellens, K. ; Tielens, H. ; Favia, P. ; Rohr,

Author_Institution

imec, Leuven, Belgium

fYear

2011

fDate

5-7 Dec. 2011

Abstract

This paper presents for the first time a low-complexity high performance CMOS HK/MG process on planar bulk Si using a single dielectric / single metal gate stack and making use of dual-channel integration. Through the optimization of the Si₄₅Ge₅₅/Si cap deposition and the workfunction metal, high performance devices with balanced V_t,sat (+0.12V, -0.16V) at scaled T_inv~1nm and gate length L_g~30nm are reported, leading to 17ps ring oscillators at 1μW/stage at Vdd=0.7V. Compatibility with gate last processing is also demonstrated.

Keywords

CMOS integrated circuits; Ge-Si alloys; elemental semiconductors; oscillators; silicon; CMOS HK-MG process; CMOS gate-first integration; CMOS gate-last integration; Si₄₅Ge₅₅-Si; cap deposition; cap-free single metal gate; dual-channel integration technology; ring oscillator; single dielectric-single metal gate stack; time 17 ps; voltage -0.16 V; voltage 0.12 V; voltage 0.7 V; CMOS integrated circuits; Dielectrics; Logic gates; MOS devices; Metals; Performance evaluation; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting (IEDM), 2011 IEEE International

Conference_Location

Washington, DC

ISSN

0163-1918

Print_ISBN

978-1-4577-0506-9

Electronic_ISBN

0163-1918

Type

conf

DOI

10.1109/IEDM.2011.6131633

Filename

6131633