Title :
A 30 ns 64 Mb DRAM with built-in self-test and repair function
Author :
Koike, H. ; Tanabe, A. ; Takeshima, T. ; Aimoto, Y. ; Takada, M. ; Ishijima, T. ; Kasai, N. ; Hada, H. ; Shibahara, K. ; Kunio, T. ; Tanigawa, T. ; Saeki, T. ; Sakao, M. ; Miyamoto, H. ; Nozue, H. ; Ohya, S. ; Murotani, T. ; Koyama, K. ; Okuda, T.
Author_Institution :
NEC Corp., Kanagawa, Japan
Abstract :
A 64 Mw*1 b/16 Mw*4 b DRAM with 30-ns access time which uses a double-metal layer and 0.4- mu m CMOS technology is reported. The external power supply is 3 V, while memory cell arrays operate at 2.2 V. Key circuits for the 64-Mb DRAM are (1) a latched-sense, shared-sense circuit with open bit-line read-out and folded bit-line rewrite operations (LOF) to reduce inter-bit-line coupling noise, (2) alternatively activated and separately end-located word drivers and X decoders to reduce word-line selection delay, and (3) built-in self test and repair circuits using spare memory cells to reduce test costs and increase chip reliability.<>
Keywords :
CMOS integrated circuits; DRAM chips; VLSI; built-in self test; redundancy; reliability; 0.4 micron; 1 bit; 2.2 V; 3 V; 30 ns; 4 bit; 64 Mbit; CMOS; DRAM; ULSI; access time; built-in self-test; double-metal layer; folded bit-line rewrite; inter-bit-line coupling noise; latched-sense; open bit-line read-out; reliability; repair function; shared-sense circuit; spare memory cells; Automatic testing; Built-in self-test; CMOS technology; Circuit noise; Circuit testing; Coupling circuits; Driver circuits; Noise reduction; Power supplies; Random access memory;
Conference_Titel :
Solid-State Circuits Conference, 1992. Digest of Technical Papers. 39th ISSCC, 1992 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0573-6
DOI :
10.1109/ISSCC.1992.200456
