DocumentCode :
3039297
Title :
Intellectual Property Protection of IP Cores at HDL Design Level with Automatic Signature Spreading
Author :
Castillo, E. ; Parrilla, L. ; Garcia, Alvaro ; Meyer-Baese, U. ; Lloris, A.
fYear :
2008
fDate :
Sept. 29 2008-Oct. 4 2008
Firstpage :
26
Lastpage :
31
Abstract :
Watermarking techniques for Intellectual Property Protection (IPP) of IP cores at the HDL design level are proposed in this paper. The basic idea relies on spreading the bits of a digital signature at the HDL design level using combinational logic or look-up structures included within the original system. The techniques also include a secure and non-destructive signature extraction process. Furthermore, in this work the applicability has been extended due to the development of an automated tool for signature spreading purposes. Advances in the automated tool have been achieved by including new search algorithms, as the Simulated Annealing algorithm that achieves additional resources optimization while maintains reduced computation times. A detailed study of the research algorithms is carried out in order to show the advantages in terms of design effort, additional resources and execution times.
Keywords :
hardware description languages; industrial property; watermarking; HDL design level; IP cores; automatic signature spreading; combinational logic; intellectual property protection; look-up structures; watermarking techniques; Application software; Copyright protection; Data mining; Digital signatures; Hardware design languages; Intellectual property; Logic design; Multiplexing; Proposals; Watermarking; FPGAs; IP cores; intellectual property protection; watermarking;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Advances in Electronics and Micro-electronics, 2008. ENICS '08. International Conference on
Conference_Location :
Valencia
Print_ISBN :
978-0-7695-3370-4
Electronic_ISBN :
978-0-7695-3370-4
Type :
conf
DOI :
10.1109/ENICS.2008.29
Filename :
4641230
Link To Document :
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