Efficient Scan-Based BIST Scheme for Low Power Testing of VLSI Chips

Author

Shah, Malav

Author_Institution

Dhirubhai Ambani Inst. of Inf. & Commun. Technol., Gujarat

fYear

2006

fDate

4-6 Oct. 2006

Firstpage

376

Lastpage

381

Abstract

It is seen that power dissipation during test mode is quite high compared to that during the functional mode of operation of a digital circuit. This may lead to damage of certain chips only because they are tested, leading to unnecessary loss of yield. This paper presents a simple yet efficient low power scheme for scan-based BIST. It reduces test length and switching-activity in CUTs reducing power dissipation during test mode without compromising fault coverage. Experiments conducted on ISCAS89 benchmark circuits demonstrate that proposed scheme gives better fault coverage with a large reduction in transitions reducing power dissipation during testing

Keywords

VLSI; automatic test pattern generation; built-in self test; fault simulation; integrated circuit design; integrated circuit testing; low-power electronics; BIST scheme; CUT; ISCAS89 benchmark circuits; VLSI chips; digital circuit; fault coverage; functional operation mode; low power testing; partial scan; power dissipation; switching-activity; test length; test-per-clock; test-per-scan; Benchmark testing; Built-in self-test; Circuit faults; Circuit noise; Circuit testing; Integrated circuit reliability; Power dissipation; Registers; Switching circuits; Very large scale integration; Design; Reliability; Scan; partial scan; switching activity; test length; test-per-clock; test-per-scan;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design, 2006. ISLPED'06. Proceedings of the 2006 International Symposium on

Conference_Location

Tegernsee

Print_ISBN

1-59593-462-6

Type

conf

DOI

10.1109/LPE.2006.4271872

Filename

4271872