Title :
A 5 V-only 0.6 mu m flash EEPROM with row decoder scheme in triple-well structure
Author :
Kuriyama, M. ; Atsumi, S. ; Umezawa, A. ; Banba, H. ; Imamiya, K.I. ; Naruke, K. ; Yamada, S. ; Obi, E. ; Oshikiri, M. ; Suzuki, T. ; Wada, M. ; Tanaka, S.
Author_Institution :
Toshiba Corp., Kawasaki, Japan
Abstract :
An experimental 4-Mb flash EEPROM realizes 5-V-only operation by introducing a compact row decoder with a triple-well structure. Since the cell-source voltage during erase is only 5 V, high source-junction breakdown voltage is not necessary, making a smaller cell feasible. By optimizing memory cell implant, fast programming is achieved with 5 V drain voltage. A simple stable EEPROM redundancy circuit reduces chip test cost and has minimum effect on chip size compared with a polysilicon redundancy circuit. The chip is packaged in a 48-spin cerdip.<>
Keywords :
CMOS integrated circuits; EPROM; VLSI; integrated memory circuits; packaging; 0.6 micron; 4 Mbit; 48-spin cerdip; 5 V; CMOS; ULSI; cell-source voltage; chip size; fast programming; flash EEPROM; memory cell implant; redundancy circuit; row decoder scheme; source-junction breakdown voltage; test cost; triple-well structure; Charge pumps; Decoding; EPROM; Low voltage; Solid state circuits; Very large scale integration;
Conference_Titel :
Solid-State Circuits Conference, 1992. Digest of Technical Papers. 39th ISSCC, 1992 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0573-6
DOI :
10.1109/ISSCC.1992.200457
