A 155 MHz clock recovery delay- and phase-locked loop

The authors describe a completely monolithic delay-locked loop (DLL) which may be used either by itself as a deskewing element or in conjunction with an external voltage-controlled crystal oscillator (VCXO) for a delay- and phase-locked loop (D/PLL) that enables jitter-peaking-free clock recovery by removing the zero from the forward path. The voltage-controlled phase shifter (VCPS) shifts incoming data under loop control to align the data with the clock. The loop amplifier is an integrator so that the DLL is first order. The bandwidth of the loop determines the frequencies over which input jitter may be tracked out. The phase detector is a pattern-and duty-cycle insensitive implementation. The higher-order poles provide additional filtering of phase-detector output ripple to further improve jitter accommodation.<>