Title :
Analysis of dynamic retention characteristics of NWL scheme in high density DRAM
Author :
Myungjae Lee ; Hyungshin Kwon ; Jonghyoung Lim ; Hongsun Hwang ; SeongJin Jang ; Yonghan Roh
Author_Institution :
Sch. of Inf. & Commun. Eng., SungKyunKwan Univ., Suwon, South Korea
Abstract :
A Negative Word Line (NWL) bias scheme is an effective method to reduce the junction leakage current of DRAM cell transistor by reducing the channel implantation dose used to adjust the threshold voltage. However, the static data retention characteristics might be degraded by the GIDL current due to increasing E-filed between the gate and the drain in off-state. In addition, it could cause degradation of the dynamic data retention characteristics by occurring negative word line bias (VNWL) fluctuation during DRAM chip operation, because of increase of the sub-threshold leakage current of cell transistor. This paper gives a detailed analysis of the problem on the dynamic chip test in NWL scheme, especially for the Refresh Cycle Reduction (RCR) mode test and suggests the design guideline for the chip test.
Keywords :
DRAM chips; integrated circuit testing; leakage currents; DRAM cell transistor; DRAM chip operation; E-filed; GIDL current; NWL bias scheme; RCR mode test; VNWL fluctuation; channel implantation dose reduction; dynamic chip test; dynamic data retention characteristics; high-density DRAM; junction leakage current reduction; negative word line bias scheme; refresh cycle reduction mode test; static data retention characteristics; subthreshold leakage current; threshold voltage; Electron devices; Failure analysis; Generators; High definition video; Random access memory; System-on-chip;
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits (IPFA), 2013 20th IEEE International Symposium on the
Conference_Location :
Suzhou
Print_ISBN :
978-1-4799-1241-4
DOI :
10.1109/IPFA.2013.6599242
