Efficient fault detection scheme for reliable AES architecture

Cryptography plays an important role in the security of data transmission. The Advanced Encryption Standard (AES) is the newly accepted symmetric cryptography standard for transferring block of data securely. However, the faults that accidently or maliciously occur in the hardware implementation of this standard may cause erroneous encrypted/decrypted output that results in losing the original message and/or leaking the secret key information. In this paper, concurrent structure independent fault detection schemes for designing high performance and reliable architecture of the AES is presented. For high performance applications, instead of using look-up tables alone for the implementation of S-box and inverse S-box and their parity predictions, logic gate implementations based on composite fields are also utilized. For the reliability, operation are performed independent of the method the S-box is implemented. The proposed schemes can be applied to both the LUT and composite field implementations. Moreover, the overhead costs, including space complexity and time delay of the proposed schemes are analyzed and compared with their counterparts. Finally, our simulation results show the error coverage of greater than 99 percent for the proposed schemes.