Title :
A 6 ns 4 Mb ECL I/O BiCMOS SRAM with LV-TTL mask option
Author :
Nakamura, K. ; Oguri, T. ; Atsumo, T. ; Takada, M. ; Ikemoto, A. ; Suzuki, H. ; Nishigori, T. ; Yamazaki, T.
Author_Institution :
NEC Corp., Sagamihara, Japan
Abstract :
The authors report on a 4-Mb BiCMOS SRAM which achieves 6-ns and 8-ns access times with ECL (emitter coupled logic) and TTL (transistor-transistor logic) I/O interfaces, respectively, using: (1) a BinMOS converter directly connecting the ECL level to the CMOS level, (2) a high-speed BinMOS circuit with low-threshold voltage nMOSFETs, (3) an optimum word decoder, and (4) high-speed bipolar sensing circuits with a 3.3-V supply. The SRAM is applicable to either an ECL 100 K interface (VCC=0 V, VEE=4.5 V) or an LV-TTL interface (VCC=3.3 V, VEE=0 V), depending on the mask option used.<>
Keywords :
BiCMOS integrated circuits; SRAM chips; VLSI; emitter-coupled logic; transistor-transistor logic; 3.3 V; 4 Mbit; 4.5 V; 6 to 8 ns; BiCMOS SRAM; BinMOS converter; ECL 100 K interface; ECL I/O; I/O interfaces; LV-TTL interface; LV-TTL mask option; TTL I/O; ULSI; access times; emitter coupled logic; transistor-transistor logic; BiCMOS integrated circuits; CMOS logic circuits; Capacitance; Decoding; Delay effects; Equations; MOSFETs; Power supplies; Random access memory; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 1992. Digest of Technical Papers. 39th ISSCC, 1992 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0573-6
DOI :
10.1109/ISSCC.1992.200487
