Title :
Design of a custom processing unit based on Intel i486 architectures and performances trade-offs
Author_Institution :
Commun. Syst. Lab., La Gaude, France
Abstract :
The architecture of a customized processing unit using an Intel i486 microprocessor as an efficient general-purpose processor is described. The objectives for the optimization of the i486 performances are: the design of a set of customized support chips to control the processor bus, the memory management, the arbitrations, the interrupts, and the I/O data transfer; the use of 80-ns DRAM (dynamic random access memory) 4 Mb modules; and an arbitration scheme that prioritizes DMA (direct memory access) data transfer at a sustained rate of 10 MB/s. System performance variation due to critical design parameters such as cache hit rate and memory access time is analyzed with a detailed simulation model of the complete processor system
Keywords :
DRAM chips; computer architecture; microprocessor chips; performance evaluation; storage management chips; 4 Mb modules; 40 Mbit/s; 80 ns; 80-ns DRAM; I/O data transfer; Intel i486 architectures; arbitrations; cache hit rate; custom processing unit; customized support chips; direct memory access; general-purpose processor; interrupts; memory access time; memory management; performances trade-offs; processor bus; simulation model; Availability; CMOS technology; DRAM chips; Decoding; Error correction codes; Memory management; Pins; Random access memory; Read-write memory; System-on-a-chip;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1990. ICCD '90. Proceedings, 1990 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-2079-X
DOI :
10.1109/ICCD.1990.130281
