Multiprocessor SoC Implementation of Neural Network Training on FPGA

Software implementations of artificial neural networks (ANNs) and their training on a sequential processor are inefficient because they do not take advantage of parallelism. ASIC and FPGA implementations employ specific hardware structures to exploit parallelism in order to improve processing speed; however, optimizing resource usage requires the use of fixed-point arithmetic, thereby losing precision, and the final system is restricted to a particular network topology. This paper presents a mixed approach based on a multiprocessor system-on-chip (SoC) on a FPGA. The use of software-driven embedded microprocessors with custom floating-point extensions for ANN related functions allows for greater precision and flexibility in the structure of the networks to be trained with no need for device reconfiguration, and parallelism is achieved by the use of a large number of processing units. Design limitations are discussed, and preliminary results are presented on the performance of the system on an Altera DE2-70 development board.