Realization of vertical resistive memory (VRRAM) using cost effective 3D process

Author

Baek, I.G. ; Park, C.J. ; Ju, H. ; Seong, D.J. ; Ahn, H.S. ; Kim, J.H. ; Yang, M.K. ; Song, S.H. ; Kim, E.M. ; Park, S.O. ; Park, Cheong Hee ; Song, C.W. ; Jeong, G.T. ; Choi, S. ; Kang, H.K. ; Chung, C.

Author_Institution

New Memory Lab., Samsung Electron. Co., Ltd., Hwasung, South Korea

fYear

2011

fDate

5-7 Dec. 2011

Abstract

Vertical ReRAM (VRRAM) has been realized with modification of Vertical NAND (VNAND) process and architecture as a cost-effective and extensible technology for future mass data storage. Dedicated ALD/CVD deposition and wet etching processes were developed to reproduce planar ReRAM properties in VRRAM structure. Multi-stack of VRRAM cell layers were fabricated at the same time using ALD TaOx/barrier layer/CVD TiN cell stacks. Oxidation control without intermixing has been found very critical in the vertical ReRAM cell process.

Keywords

NAND circuits; atomic layer deposition; chemical vapour deposition; etching; oxidation; random-access storage; tantalum compounds; titanium compounds; ALD/CVD deposition; CVD TiN cell stacks; TaO_x; TiN; VNAND process; VRRAM cell layers; VRRAM structure; barrier layer; cost effective 3D process; mass data storage; oxidation control; planar ReRAM properties; vertical NAND process; vertical ReRAM; vertical resistive memory; wet etching; Computer architecture; Electrodes; Helium; Resistance; Switches; Three dimensional displays; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting (IEDM), 2011 IEEE International

Conference_Location

Washington, DC

ISSN

0163-1918

Print_ISBN

978-1-4577-0506-9

Electronic_ISBN

0163-1918

Type

conf

DOI

10.1109/IEDM.2011.6131654

Filename

6131654