DocumentCode :
3040055
Title :
First experimental demonstration of gate-all-around III–V MOSFETs by top-down approach
Author :
Gu, J.J. ; Liu, Y.Q. ; Wu, Y.Q. ; Colby, R. ; Gordon, R.G. ; Ye, P.D.
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
fYear :
2011
fDate :
5-7 Dec. 2011
Abstract :
The first inversion-mode gate-all-around (GAA) III-V MOSFETs are experimentally demonstrated with a high mobility In0.53Ga0.47As channel and atomic-layer-deposited (ALD) Al2O3/WN gate stacks by a top-down approach. A well-controlled InGaAs nanowire release process and a novel ALD high-k/metal gate process has been developed to enable the fabrication of III-V GAA MOSFETs. Well-behaved on-state and off-state performance has been achieved with channel length (Lch) down to 50nm. A detailed scaling metrics study (S.S., DIBL, VT) with Lch of 50nm - 110nm and fin width (WFin) of 30nm - 50nm are carried out, showing the immunity to short channel effects with the advanced 3D structure. The GAA structure has provided a viable path towards ultimate scaling of III-V MOSFETs.
Keywords :
III-V semiconductors; MOSFET; alumina; atomic layer deposition; gallium arsenide; indium compounds; nanowires; ALD high-k/metal gate process; In0.53Ga0.47As-Al2O3; atomic-layer-deposited gate stacks; gate-all-around MOSFET; high mobility channel; nanowire release process; size 30 nm to 110 nm; top-down approach; Aluminum oxide; Indium gallium arsenide; Logic gates; MOSFETs; Measurement; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting (IEDM), 2011 IEEE International
Conference_Location :
Washington, DC
ISSN :
0163-1918
Print_ISBN :
978-1-4577-0506-9
Electronic_ISBN :
0163-1918
Type :
conf
DOI :
10.1109/IEDM.2011.6131662
Filename :
6131662
Link To Document :
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